About the Role
This is an ASIC Design and STA Engineer role located in Bengaluru, India. The complete and specific details regarding team activities, detailed duties, and specific nice-to-have qualifications could not be extracted because the dedicated job detail page content was not provided in the input. An ASIC Design and STA (Static Timing Analysis) Engineer is typically responsible for the design, verification, and timing closure of Application-Specific Integrated Circuits (ASICs). This involves working on RTL design, synthesis, place and route, and performing extensive static timing analysis to ensure the circuit meets performance specifications. Strong knowledge of digital design, Verilog/VHDL, and industry-standard EDA tools is crucial. This role is fundamental to the development of high-performance and reliable semiconductor products.