Physical Design / Backend STA Engineer

About the Role

A Physical Design / Backend STA Engineer at NVIDIA would be responsible for the physical implementation of complex integrated circuits, focusing on the backend design aspects and Static Timing Analysis (STA). This involves tasks such as floorplanning, power grid design, placement, clock tree synthesis, routing, and sign-off checks, including timing closure. The role is critical in ensuring high-performance and power-efficient GPU and SoC designs. The engineer will work with cutting-edge technologies and methodologies to deliver next-generation products, collaborating with design, architecture, and verification teams to meet stringent performance, power, and area targets.

Responsibilities

• Perform physical design tasks including floorplanning, power grid design, placement, and routing.
• Conduct Static Timing Analysis (STA) to ensure timing closure across various corners and modes.
• Implement clock tree synthesis (CTS) and optimize clock networks.
• Perform physical verification checks (DRC/LVS/ERC).
• Collaborate with front-end design, DFT, and architecture teams for design integration and issue resolution.
• Develop and maintain scripts for design automation and flow enhancement.
• Contribute to design methodology improvements and best practices.

Requirements

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
• 3+ years of experience in ASIC physical design.
• Strong understanding of Static Timing Analysis (STA) concepts and tools.
• Experience with industry-standard EDA tools (e.g., Synopsys ICC/Innovus, Primetime, Tempus, Cadence Innovus, Mentor Graphics Calibre).
• Proficiency in scripting languages (e.g., Tcl, Python, Perl).
• Knowledge of advanced technology nodes (e.g., 7nm, 5nm).

Qualifications

• Experience with low-power design techniques.
• Familiarity with formal verification methods.
• Strong problem-solving and analytical skills.
• Excellent communication and teamwork abilities.