About the Role
NVIDIA is seeking a highly skilled and dedicated Physical Design Power Optimization and Modeling Engineer to become an integral part of our esteemed Networking Silicon Power engineering team. In this role, you will be instrumental in the development of cutting-edge high-speed communication devices, focusing on achieving the highest throughput, lowest latency, and optimal power efficiency. This is an exciting opportunity to contribute to the design of groundbreaking and innovative chips within a dynamic, growing, and highly professional environment. You will play a significant part in a technology-focused company known for its forward-thinking approach. If you are a creative and autonomous engineer who thrives on challenges and is ready to make a substantial impact, this role offers the chance to grow and excel as part of the industry's best physical design team.
Responsibilities
- Power Optimization of Physical design, of blocks/top-level/fc under challenging constraints.
- Optimization involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise fixes.
- Power estimation and power modeling.
Requirements
- B.SC./ M.SC. or equivalent experience in Electrical Engineering/Computer Engineering.
- 1+ years of experience in physical design and/or BE power optimization aspects.
- Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.).
- Native ability to leverage modern AI tools to accelerate engineering workflows, productivity, and problem-solving.
- Excellent problem-solving, partnership, and interpersonal skills.
Qualifications
- Knowledge in physical design flows and methodologies (PNR, STA, physical verification).
- FE design experience.
Benefits
Not specified.