About the Role
NVIDIA is seeking a Senior DFT Engineer to focus on Design for Testability (DFT) for our core silicon IP blocks. In this crucial role, you will be responsible for defining, implementing, and verifying DFT solutions for complex digital circuits that form the foundation of NVIDIA's GPUs and SoCs. You will work closely with core design teams, architects, and test engineers to ensure that our IP blocks achieve high test coverage, are easily testable in manufacturing, and meet aggressive yield targets. Your responsibilities will include developing DFT architectures, implementing scan chains, MBIST for embedded memories, and other DFT features, as well as performing extensive DFT verification using industry-standard tools. This position offers a challenging opportunity to contribute to the quality and manufacturability of NVIDIA's most advanced silicon designs, directly impacting our ability to deliver innovative products to market.
Responsibilities
- Architect and implement DFT solutions for core IP blocks
- Integrate scan, MBIST, and other DFT features into digital designs
- Develop and execute DFT verification plans for core IP
- Collaborate with RTL designers and test engineers to ensure testability
- Drive DFT sign-off and support pattern generation
Requirements
- BS or MS in Electrical Engineering or Computer Engineering
- 5+ years of experience in DFT design and verification for complex digital cores
- Expertise in scan, MBIST, and JTAG methodologies
- Proficiency with industry-standard DFT tools (e.g., Tessent, Synopsys DFT Compiler)
- Strong understanding of digital design and VLSI concepts
Qualifications
- Experience with advanced fault models and coverage analysis
- Familiarity with logic BIST and repair mechanisms
- Knowledge of post-silicon debug and diagnosis
- Experience with scripting languages (e.g., Perl, Tcl, Python)
Benefits
Not specified